A 2.4 GHz LC-VCO Fractional-N Phase-Locked Loop Open-Source Design in 130-nm BiCMOS
Published in IEEE Xplore
B.Sc. Eng. (Hons) graduate in Electronic & Telecommunication Engineering (First Class Honours) from the University of Moratuwa. I design PLLs, VCOs and on-chip passives in open-source silicon flows, and build quantized neural networks for FPGAs, a combination that draws me toward AI-assisted IC design.

Published in IEEE Xplore
Accepted at IEEE ITSC 2026
Full-custom PLLs, LC and ring VCOs, ΔΣ modulators and custom spiral inductors, taken from schematic through layout, DRC/LVS, PEX and post-layout verification.
Low-bit quantized CNNs deployed on FPGAs with Brevitas and Xilinx FINN, including a real-time license plate recognition system running at 11.5 FPS on a Kria KV260.
Labs and tutorials in analog and digital electronics and IC design at the University of Moratuwa, and the Level 4 VLSI Design module at Curtin University Colombo.